1. Field of the Invention
This invention relates to electronic frequency divider or counter circuits, and more particularly to a static, switched-latch frequency divider circuit particularly adapted for implementation in complimentary metal oxide semiconductor technology.
2. Description of Related Art
In many instances in digital electronics, it is desirable to divide a clock frequency by N where N is an integer greater than or equal to two. Power of two divider or counter circuits are fairly well-known. Odd-number counter circuits (that is, where N is an odd-integer greater than or equal to three) are somewhat more complex circuits. Such circuits often are used in electronic watch or clock circuits.
Prior art odd-number divider circuits have often been devised from random logic out of component parts such as flip-flops and simple gate circuitry. Such circuits are not normally suitable for direct implementation as part of a large scale integrated circuit because they require a large amount of random logic to reset them at the desired odd count, and therefore do not lay out on an integrated circuit in an efficient manner.
The assignee of the present invention has previously developed a family of dividers that divide by odd numbers. One such divider is shown in FIG. 1. This divide-by-three counter uses an overdriven latch architecture. The advantages of this implementation over the discrete circuit structure of the prior art are reduced transistor counts and reduced random logic. Hence, greater layout efficiency in creating integrated circuits is achieved. However, the overdriven latch architecture shown in FIG. 1, while suitable at low frequencies and high power supply voltages, suffers from at least three limitations at high frequencies and low power supply voltage.
First, the overdriven latch architecture is relatively slow because of the time required for an inverter to drive through a transmission gate and overdrive a latch. Second, such circuits use an undesirable amount of power because the latches are forced (or "overdriven") into an opposite state. Third, such circuits require critical device ratioing to guarantee that the latches can be overdriven at all combinations of supply voltages, threshold voltages, and temperatures. The threshold voltage problem becomes acute when the power supply voltage is reduced for a low power circuit. The threshold voltage becomes a dominant factor, and to guarantee that the latches can be overdriven device ratios become unrealistic and layout efficiency is reduced for integrated circuit implementation.
The present invention eliminates the necessity for device ratioing by applying a static switched-latch principle. This divider architecture has improved speed and power characteristics over the overdriven latch scheme and is more efficient for layout purposes in fabricating integrated circuits.
It is therefore an object of the present invention to provide a new and improved static switched-latch divider circuit which is particularly well configured for implementation in an integrated circuit. It is another object of the present invention to adapt such a circuit as an odd-number divider or counter. The present invention achieves these objectives with a simple, highly regular complimentary metal oxide semiconductor (CMOS) field effect transistor (FET) circuit, described in full below.